3-D stacked and aligned processors forming a logical processor with power modes controlled by respective set of configuration parameters

ABSTRACT

Methods are provided to operate a processor device in one of multiple power operating modes. The processor device comprises first and second processor chips connected in a stacked configuration, and which respectively include first and second processors that operate as a single logical processor. A control system generates control signals and different sets of configuration parameters. A first control signal is generated to input a first set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a first power operating mode wherein the first processor is turned on and the second processor is turned off. A second control signal is generated to input a second set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a second power operating mode wherein both the first processor and the second processor are turned on.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. patent application Ser. No.13/452,040, filed on Apr. 20, 2012, the disclosure of which isincorporated herein by reference.

TECHNICAL FIELD

The field relates generally to three-dimensional (3-D) multiprocessordevices that are formed by connecting processors in a stackedconfiguration, and methods for controlling 3-D stacked multiprocessordevices to selectively operate in one of a plurality of operating modes.

BACKGROUND

In the field of semiconductor processor chip fabrication, single-chipprocessors were fabricated by many companies during the early stages ofprocessor technology. In the last decade or so, as Moore's Law hascontinued to shrink dimensions, many companies and other entities havedesigned processor chips with multiple processors on a single layer.However, as the number of processors per chip continues to increase, onchip communication between processors becomes problematic. For example,as the 2D size of the processor chip increases to accommodate moreprocessors, the length of the horizontal wiring between the processorsincreases (in the range of mm or cm) resulting in cycle delays in thecommunication between processors, and requiring the use of high-poweredon-chip drivers along communication paths between processors.Furthermore, the cycle delay with respect to communication betweenprocessors increases as the operating frequency increases.

SUMMARY OF THE INVENTION

Exemplary embodiments of the invention generally includethree-dimensional (3-D) processor devices that are formed by connectingprocessors in a stacked configuration, and methods for controlling 3-Dstacked multiprocessor devices to selectively operate in one of aplurality of operating modes.

In one exemplary embodiment of the invention, a semiconductor deviceincludes a first processor chip comprising one or more processors, asecond processor chip comprising one or more processors, and a pluralityof input/output ports. The first and second processor chips areconnected in a stacked configuration and commonly share the plurality ofinput/output ports. In various exemplary embodiments of the invention,the first and second processor chips may be substantially the same. Thefirst and second processor chips may be mounted face-to-back orface-to-face.

In another exemplary embodiment of the invention, the device includes amode control circuit to selectively operate the semiconductor device inone of a plurality of operating modes to control power of thesemiconductor device. For example, the semiconductor device isselectively operable in a first mode wherein the first processor chip isturned on and the second processor chip is turned off, wherein in thefirst mode, each processor of the first processor chip is turned on andoperating at full power.

In another exemplary embodiment of the invention, the semiconductordevice may be selectively operable in a second mode wherein both thefirst and second processor chips are turned on, wherein in the secondmode, each processor of the first and second processor chips operates atless than full power so that a total power of the semiconductor devicein the second mode is substantially the same as a total power of thesemiconductor device when each processor of only the first processorchip or the second processor chip operates at full power.

In yet another exemplary embodiment of the invention, a semiconductorpackage includes a package substrate comprising electrical wiring, and aplurality of 3-D stacked processor chips mounted on the packagesubstrate. Each of the 3-D stacked processor chips includes a firstprocessor chip mounted on the package substrate, the first processorchip comprising one or more processors, a second processor chip mountedon top of the first processor chip, the second processor chip comprisingone or more processors, and a plurality of input/output ports connectedto the electrical wiring on the package substrate, wherein the first andsecond processor chips commonly share the plurality of input/outputports.

In another exemplary embodiment of the invention, a method for operatinga computer processor is provided, wherein the computer processorincludes a first processor chip and a second processor chip connected ina stacked configuration, wherein the first and second processor chipseach comprise one or more processors, The method includes selectivelygenerating one of a plurality of control signals to operate the computerprocessor in one of a plurality of operating modes to control power ofthe computer processor, wherein selectively generating one of aplurality of control signals includes generating a first control signalto operate the computer processor in a first mode wherein the firstprocessor chip is turned on and the second processor chip is turned off,and generating a second control signal to operate the computer processorin a second mode wherein both the first and second processor chips areturned on.

In one exemplary embodiment of the invention, the first and secondcontrol signals modulate a power supply voltage level applied to thefirst and second processor chips. In another exemplary embodiment of theinvention, the first and second control signals modulate an operatingfrequency of the first and second processor chips.

These and other exemplary embodiments, features, objects and advantagesof the present invention will become apparent from the followingdetailed description of illustrative embodiments thereof, which is to beread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic perspective view of a multiprocessor chip.

FIG. 2 is a schematic perspective view of a 3-D stacked multiprocessorstructure according to an exemplary embodiment of the invention.

FIG. 3 is a schematic view of a chip package structure.

FIG. 4 conceptually illustrates a 3-D stacked multiprocessor structureaccording to another exemplary embodiment of the invention.

FIG. 5 schematically illustrates a physical implementation of a 3-Dstacked multiprocessor structure, which is based on the conceptualimplementation shown in FIG. 4, according to another exemplaryembodiment of the invention.

FIG. 6 schematically illustrates a method for controlling multimodaloperation of a 3-D stacked multiprocessor structure, according to anexemplary embodiment of the invention.

FIG. 7 is a schematic plan view of a processor to which principles ofthe invention may be applied.

FIG. 8 is a schematic perspective view of a 3-D stacked multiprocessordevice comprising a pair of processors having identical processorlayouts as depicted in FIG. 7, according to an exemplary embodiment ofthe invention.

FIG. 9A is a schematic perspective view of a 3-D stacked multiprocessordevice comprising first and second processors vertically stacked on topof each other having aligned L2 and L3 caches, according to an exemplaryembodiment of the invention.

FIG. 9B is a schematic perspective view of the 3-D stackedmultiprocessor device of FIG. 9A having the L3 caches conjoined foroperation as a shared L3 cache by the first and second processors,according to an exemplary embodiment of the invention.

FIG. 9C is a schematic perspective view of the 3-D stackedmultiprocessor device of FIG. 9A having the L3 caches as well as L2caches conjoined for operation as a shared L2 cache and shared L3 cacheby the first and second processors, according to an exemplary embodimentof the invention.

FIG. 10 is a schematic perspective view of a 3-D stacked multiprocessordevice according to yet another exemplary embodiment of the invention.

FIG. 11 schematically illustrates communication paths between variouscomponents of the processors shown in FIG. 10, according to an exemplaryembodiment of the invention.

FIG. 12 schematically illustrates a processor interconnect structure fora planar processor system.

FIG. 13 schematically illustrates a processor interconnect structure fora 3-D stacked multiprocessor system according to an exemplary embodimentof the invention.

FIG. 14 schematically illustrates a processor interconnect structure fora 3-D stacked multiprocessor system according to another exemplaryembodiment of the invention.

FIG. 15 is a schematic top perspective view of a 3-D stackedmultiprocessor system according to an exemplary embodiment of theinvention having a processor interconnect structure that is based on theprocessor interconnect structure of FIG. 14.

FIG. 16 schematically illustrates a processor interconnect structure fora 3-D stacked multiprocessor system according to yet another exemplaryembodiment of the invention.

FIG. 17A schematically illustrates two processors having identicallayouts according to an exemplary embodiment of the invention, whereincorresponding regions of the two identical processors are identified asbeing faster or slower than its counterpart region.

FIG. 17B schematically illustrates a 3-D stacked processor structurethat is formed by vertically stacking the two processors shown in FIG.17A, and operated as a single processor that is composed of the fastestof the corresponding regions of each processor, according to anexemplary embodiment of the invention.

FIG. 18 schematically illustrates a method for implementing run-aheadfunctionality in a 3-D stacked processor system, according to anexemplary embodiment of the invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the invention will now be described in furtherdetail with regard to 3-D multiprocessor devices that are formed byconnecting processors in a stacked configuration, and methods forcontrolling 3-D stacked multiprocessor devices to selectively operate inone of multiple resource aggregating and sharing modes.

FIG. 1 is a schematic perspective view of a multiprocessor chip to whichprinciples of the invention may be applied. In particular, FIG. 1schematically illustrates a multiprocessor chip 10 comprising asemiconductor die 12 having a plurality of processors C1, C2, . . . ,C49 (generally denoted Cn) formed on the die 12. The processors Cn arearranged in a “planar” system, wherein each processor Cn has its owndedicated footprint in a 2-D space. The processors Cn may be connectedto each other in the 2-D plane using horizontal wiring and electricalinterconnects that are formed as part of the BEOL (back end of line)structure of the chip 10, as is readily understood by those of ordinaryskill in the art.

In a planar system as shown in FIG. 1, as the number of processorsincreases, communication between processors becomes problematic. Forexample, as the 2D size of chip increases to accommodate moreprocessors, the length of the horizontal wiring between the processorsincreases (in the range of mm or cm) resulting in cycle delays in thecommunication paths between processors. This cycle delay requires theuse of high-powered on-chip drivers along the communication pathsbetween processors. Furthermore, this cycle delay also increases withincreasing operating frequency.

Principles of the invention utilize chip-stacking techniques to form 3-Dstacked multiprocessor structures using multiple layers of processorchips wherein two or more processor chips are integrated into a singlestacked system having a single-chip “footprint” (i.e., the stackedprocessor chips appear to be a single chip). The term “processor chip”as used herein refers to any semiconductor chip or die having one ormore processors. The term “multiprocessor chip” as used herein refers toany semiconductor chip or die having two or more processors. In general,in a 3-D stacked structure, two or more chip layers includes processorsthat are aligned and interconnected using short vertical interconnectssuch that processors in one layer are aligned and vertically connectedto corresponding processors in another layer. It is to be understoodthat when two different processors or processor components/elements ondifferent processor chip layers are said to be “aligned” with eachother, the term “aligned’ means, for example, that the two differentprocessors or processor component/elements at least partially overlap orfully overlap each other on the different layers. In this regard, twoprocessors or components/elements of processors on different layers ofprocessor chips can be fully aligned in that the processors orcomponents are in the same 2D positions of each plane within a 3D stackof processor chips. Alternatively, the processors or components/elementsof processors may be substantially aligned but with some offset betweenthe 2D positions of each plane within the 3D stack of processor chips.

For example, FIG. 2 is a schematic perspective view of a 3-D stackedmultiprocessor structure according to an exemplary embodiment of theinvention. In particular, FIG. 2 schematically illustrates a 3-D stackedmultiprocessor chip 20 comprising a first multiprocessor chip 22A and asecond multiprocessor chip 22B vertically stacked on top of the firstmultiprocessor chip 22A. In the exemplary embodiment of FIG. 2, themultiprocessor chips 22A and 22B are substantially the same (identicalin component structure, but may vary in interconnect structure), and aredepicted as having 49 integrated processors, similar to themultiprocessor chip 10 depicted in FIG. 1. In particular, the firstmultiprocessor chip 22A comprises a plurality of processors C1A, C2A, .. . , C49A and the second multiprocessor chip 22B comprises a pluralityof processors C1B, C2B . . . , C49B. The first and second multiprocessorchips 22A and 22B are vertically stacked on one another and connected toeach other such that pairs of processors C1A/C1B, C2A/C2B, . . . ,C49A/C49B (generally, CnA/CnB) are aligned and connected to each otherusing vertical interconnects.

With the exemplary structure depicted in FIG. 2, each aligned processorstack CnA/CnB comprises a plurality of vertically connected processorsthat commonly share the same I/O connections. These I/O connections aremultiplexed internally such that at each processor location in 2D space,the plurality of vertically stacked (and connected) processors CnA/CnBlogically appear (to other stacked processors) to operate and functionas a single processor. Principles of the invention can be extended toinclude a plurality of 3-D stacked processor chips (such as shown inFIG. 2) packaged together on a package substrate. These principles willnow be discussed in further detail with reference to FIGS. 3, 4, and 5.

FIG. 3 is a schematic view of a chip package structure to whichprinciples of the invention may be applied. In particular, FIG. 3depicts a processor system 30 comprising a package substrate 32 and aplurality of processor chips P1, P2, P3, P4, P5 and P6 mounted on thepackage substrate 32. The package substrate 32 comprises a plurality ofelectrical interconnects and traces that form electrical wiring 34 whichprovides an all-to-all connection between the processor chips P1, P2,P3, P4, P5 and P6. Each of the processor chips P1, P2, P3, P4, P5, andP6 are identical and may be multiprocessor chips each having a pluralityof processors.

FIGS. 4 and 5 schematically illustrate a 3-D stacked processor systemaccording to another exemplary embodiment of the invention. Inparticular, FIG. 4 is a conceptual view of an exemplary 3-D stackedmultiprocessor package structure 40. Similar to the package structure 30depicted in FIG. 3, the 3-D stacked multiprocessor package structure 40of FIG. 4 comprises a package substrate 32 and a plurality of firstlayer processor chips P1A, P2A, P3A, P4A, P5A and P6A mounted on thepackage substrate 32. The package substrate 32 comprises a plurality ofelectrical interconnects and traces that form electrical wiring 34 whichprovides an all-to-all connection between the processor chips P1A, P2A,P3A, P4A, P5A and P6A. Each of the processor chips P1A, P2A, P3A, P4A,P5A and P6A are identical and may be multiprocessor chips each having aplurality of processors.

As further shown in FIG. 4, a plurality of second layer processor chipsP1B, P2B, P3B, P4B, P5B and P6B are vertically disposed and mounted oncorresponding first layer processor chips P1A, P2A, P3A, P4A, P5A andP6A using short vertical connections 36. The second layer of processorchips P1B, P2B, P3B, P4B, P5B and P6B are identical to the correspondingfirst layer of processor chips P1A, P2A, P3A, P4A, P5A and P6A, and maybe multiprocessor chips each having a plurality of processors. FIG. 4depicts a plurality of dotted lines 34 a that represent virtualall-to-all wiring between the processor chips P1B, P2B, P3B, P4B, P5Band P6B in the second package layer of chips. These virtual wires 34 ado not physically exist, but rather represent that the second layerprocessor chips P1B, P2B, P3B, P4B, P5B and P6B are connected to eachother and can communicate using the same physical wiring 34 that isformed on the package substrate 32.

FIG. 5 schematically illustrates a physical implementation of a 3-Dstacked multiprocessor structure 50, which is based on the conceptualimplementation shown in FIG. 4, according to another exemplaryembodiment of the invention. As depicted in FIG. 5, the only wiring thatphysically exists in the 3-D stacked multiprocessor package structure 50is the wiring 34 that is formed on the package substrate 32 and theshort vertical interconnects 36 that are formed between thecorresponding processor chip stacks P1A/P1B, P2A/P2B, P3A/P3B, P4A/P4B,P5A/P5B and P6A/P6B. In the 3-D stacked multiprocessor package structure50 of FIG. 5, the processor chips within a given vertical stack P1A/P1B,P2A/P2B, P3A/P3B, P4A/P4B, P5A/P5B and P6A/P6B will communicate witheach other using the vertical connections 36 that are formed betweenprocessor chips (and these vertical connections 36 include connectionsthat are formed between corresponding aligned processors in differentprocessor chip layers).

In accordance with exemplary embodiments of the invention, two processorchips can be conjoined using known semiconductor fabrication techniqueswherein two identical processor chips can be bonded together“face-to-back” or “face-to-face”. In a face-to-back configuration, theactive surface (face) of a first processor chip is bonded to thenon-active surface (back) of a second processor chip, wherein theprocessors and other corresponding elements of the two processor chipsare aligned. With this structure, vertical wiring (e.g., conductivevias) can be formed in the active surface of the first processor chipand exposed as a first array of contact pads on the active surface ofthe first processor chip, and vertical wiring (e.g.,through-silicon-vias) can be formed through the back side of the secondprocessor chip and exposed as a second array of contact pads on thenon-active surface of the second processor chip. The first and secondarray of contact pads can be soldered together when the first and secondprocessor chips are conjoined face-to-back, thereby forming the shortvertical connections between the aligned processor elements. To shortenthe length of the vertical connections, the back side of the secondprocessor chip can be ground down using known techniques, to make thedie thinner.

In a “face-to-face” configuration, wherein two identical processor chips(identical in function) that are mirror images of each other are bondedsuch that the active surface (face) of a first processor chip is bondedto the active surface (face) of a second processor chip, with theprocessors and other elements of the two chips aligned. With thisstructure, vertical wiring (e.g., conductive vias) can be formed in theactive surface of the first processor chip and exposed as a first arrayof contact pads on the active surface of the first processor chip, andvertical wiring can be formed in the active surface of the secondprocessor chip and exposed as a second array of contact pads on theactive surface of the second processor chip. The first and second arrayof contact pads can be soldered together when the first and secondprocessor chips are conjoined face-to-face, thereby forming shortvertical connections between the aligned processor elements.

With 3-D stacked processor systems, two or more processors that areapproximately (or literally) co-located in their planar space, but lyingon different layers, can operate independently or collaboratively byaggregating and/or sharing resources to augment functionality and topush operating thresholds, reliability, and performance further thanwhat would be practical to do in a planar system where each chip has itsown space on a 2-dimensional package. Various methods for controlling3-D stacked multiprocessors to selectively operate in one or moremultiple resource aggregating and/or sharing modes will be discussed infurther detail below with reference to FIGS. 6˜18. In general, exemplarymethods for selectively controlling 3-D stacked multiprocessors enable agroup of stacked processors to operate concurrently, yet independentlyof each other for certain applications. For other application asdiscussed below, two or more vertically stacked processors can becontrolled to selectively operate in a collaborative fashion by sharingor aggregating resources (e.g., threads, execution units, caches, etc.)across the various layers, using the short vertical connections betweenthe processor layers as fast communication paths, to provide enhancedoperation.

In accordance with exemplary embodiments of the invention, controlschemes are employed to control multimodal operation of two or morevertically stacked processors, so that the processors within a verticalstack can be selectively controlled to operate independently or in acollaborative manner. For example, FIG. 6 schematically illustrates amethod for controlling the multimodal operation of a 3-D stackedmultiprocessor structure according to an exemplary embodiment of theinvention. In particular, a control scheme 60 as shown in FIG. 6includes a multiplexer 61 that selectively receives as input a pluralityof configuration parameter sets 62 and 64 and a configuration modecontrol signal 66. The different sets of configuration parameters A andB are selectively output as machine inputs 68 to a given vertical stackof processors, wherein the machine inputs configure the processor stackto operate in one of a plurality of different operating modes asspecified by the machine inputs 68. Although two sets of inputconfiguration parameters A and B are shown for ease of illustration,three or more different sets of configuration parameters can be inputand selectively output by the multiplexer 61. It is to be understoodthat the control scheme of FIG. 6 is a system that is local to oneprocessor stack, and that each processor stack in a given processorsystem will have a corresponding control circuit as shown in FIG. 6.

The control system 60 of FIG. 6 can be controlled by global controlsystem, such as a service processor, that scans in the controlinformation and outputs a configuration control signal 66 to eachmultiplexer 61 in the processor system to configure the processor stacksin a given manner. The machine inputs 68 that are output from eachmultiplexer 61 to a corresponding processor stack can be furthermultiplexed and/or decoded using circuitry that is internal (on-chip) tothe vertically stacked processors to control various I/O ports (to beshared or bypassed) and other switches that may be employed to controlsharing and/or aggregating of resources between different layers ofprocessors in a given processor stack.

In various exemplary embodiments of the invention as discussed below,when two or more processors in a vertical stack are spatiallycoincident, the processors and their components can be synergisticallycombined in various manners to give a processor-tupled system severalnew uses to enhance performance. Initially, it is to be noted thatbecause a vertical processor stack places two or more processors (moreor less—either exactly or approximately) right on top of each other, asan initial impression, this seems impractical because it doubles theheat associated with any hotspots, which tends to be mostly located inprocessors. In this regard, exemplary control schemes may be implementedto control the power of a stack of co-located processors by running thestacked processors at a lower power level by modulating the operatingvoltage and/or the operating frequency, for example, so that the totalpower (e.g. total power density and/or total power consumption) ismanageable.

More specifically, in one exemplary embodiment of the invention, a 3Dstacked processor device, which is fabricated by vertically stacking andconnecting a plurality of processor chips, can be operated one of aplurality of operating modes to control power the 3D stacked processordevice. For example, in a 3D stacked processor device having first andsecond processor chips, the 3D stacked processor device can beselectively operated in a first mode wherein the first processor chip isturned on and a second processor chip is turned off. In the first mode,each processor of the first processor chip is turned on and may beoperating at maximum frequency and full power, with a total power thatcan be supported by the package structure (e.g., the power density atcertain hot spots is controlled so that the heat at a given hot spot inthe package is not too excessive for the given package structure.)

In another mode of operation, the 3D stacked processor device can beselectively operated in a second mode wherein both the first and secondprocessor chips are turned on. In this instance, both processor chipscan be operating at a maximum frequency and power level with a totalpower (e.g., power density or power consumption) that can be supportedby the package structure. In another instance, in the second mode ofoperation, each processor of the first and second processor chips canoperate at less than full power so that a total power of the 3D stackedprocessor device is substantially the same as the total power of the 3Dstacked processor device when each processor of only the first processorchip or second processor chips operates at full power and/or maximumfrequency. In other words, to obtain the same power consumption or powerdensity profile, the processors in each of the processor chip layers canbe operated at a lower supply voltage (or lower operating frequency) sothat the aggregate power consumption is the same or similar to the firstmode where the processors on only one processor chip layer are active.

A power control scheme according to principles of the invention is basedon a realization that the power provided to a processor can be reducedby a significant percent (e.g., 50%) while only having to decrease theoperating frequency of the processor by a much smaller amount (e.g.,10%). A power control scheme can be used to selectively control thepower supply voltage of the processors or by adjusting the frequency ofoperation, each of which serves to adjust the overall power consumptionof a processor chip. Thus, in 3-D stacked processor chip structurehaving multiple planes of processors, the ability to modulate the powersupply voltage, and selectively power-off subsets of processor planes,allows there to be a range of operating modes in the system, includingone or more modes in which multiple planes of processors are operated ata lower voltage so as to keep the total power substantially the same asthe total power consumed when operating one plane of processors (or bymaintaining the same power density at a given hotpot in the 3-D stackedprocess chip structure when operating multiple planes of processors aone plane of processors).

In a 3-D processor stack, each set of vertically stacked processors usethe same set of interconnect signals, on-package as well as off-package,in each power control operating mode. In this regard, since eachprocessor chip layer in a vertical stack shares the same interconnectsignals, even when processor chips are operating at a lower frequency(in the second mode), there is less communication requirements (less I/Obandwidth) required. As such, principles of the invention which employtechniques for reusing (multiplexing) the interconnect signals andpackage I/O signals are motivated by the lower bandwidth requirementsgenerated from each layer in the 3-D stack due to the lower frequencyoperation as demanded by the constraint to preserve the powerconsumption constant.

In other exemplary embodiments of the invention, in a processor systemcomprising two or more layers of stacked processor chips, wherein eachprocessor chip includes one or more processors, wherein processors indifferent processor chip layers are connected through verticalconnections between the different processor chip layers, a mode controlcircuit (such as shown and described above with reference to FIG. 6) canselectively configure two or more processors in different chip layers tooperate in one of a plurality of operating modes. For example, in oneoperating mode, one or more or all of the processor chips within a givenstack can be operated independently, wherein the vertical connectionsbetween layers of independently operating processor chips may be used ascommunication paths between independently operating processor chipswithin the stack.

In another mode of operation, various components/resources in differentlayers of processor chips can be aggregated to augment themicroarchitecture of one or more processors on different layers ofprocessor chips. As is readily understood by those of ordinary skill inthe art, the term “microarchitecture” of a processor refers to thephysical (hardware) configuration of a processor. The microarchitectureof a processor includes components such as caches, bus structure (pathwidth), the arrangement and number of execution units, instructionunits, arithmetic units, etc. For instance, assume a 3-D stackedprocessor chip device comprises a first processor chip having a firstprocessor, and a second processor chip having a second processor. In onemode of operation, where the first and second processor chips are bothactive, a microarchitecture of the first processor of the firstprocessor chip can be configured or augmented by aggregating elementsfrom both the first and second processors, and a microarchitecture ofthe second processor of the second processor chip can be configured oraugmented by aggregating elements from both the first and secondprocessors. In another embodiment, the first processor chip can beactive and the second processor chip can be inactive, wherein amicroarchitecture of the first processor of the active first processorchip is augmented by utilizing a portion of the second processor of theinactive second processor chip. The aggregated element may be portionsof executions units, register sets, caches, etc.

In another exemplary mode of operation, various components/resources indifferent layers of processor chips can be “shared” between differentprocessors on different layers of processor chips. For instance, asexplained below, two different processors on different layers ofprocessor chips can combine their caches (e.g., L1, L2, or L3 caches) tocreate a cache that is double in size, yet actively shared by the twoprocessors. In this instance, the aggregated (combined) components orresources are shared by the different processors. In yet anotherexemplary mode of operation, two or more different processors ondifferent layers of processor chips in a given stack can be combined tooperate a single processor image. Exemplary embodiments of the inventionshowing different modes of operation for aggregating and/or sharingand/or combining processor resources will be explained in further detailbelow with reference to FIGS. 7, 8, 9A, 9B, 9C, 10, 11, 12, 13, 14, 15,16, 17A, 17B and 18.

For example, FIGS. 7 and 8 illustrate an exemplary mode of operation forselectively configuring different processors on different layers ofprocessor chips to aggregate and/or share portions of the executionunits of the different processor to enhance the execution capabilitiesof one or more of the different processors. FIG. 7 is a schematic planview of a processor 70 to which principles of the invention may beapplied. FIG. 7 schematically illustrates a microarchitecture of aprocessor 70, wherein the processor 70 comprises various components suchas an L3 cache 71, an L2 cache 72, an execution unit 73 and aninstruction unit 74. The execution unit 73 includes a first floatingpoint unit 75 and a second floating point unit 76 (wherein the first andsecond floating point units 75 and 76 are identical) and a set offloating point registers 77. A 3-D stacked multiprocessor structure suchas shown in FIG. 8 can be constructed using a plurality of theprocessors 70 of FIG. 7.

In particular, FIG. 8 is a schematic perspective view of a 3-D stackedmultiprocessor device 80 comprising a first processor 70A and a secondprocessor 70B vertically stacked on top of the first processor 70A. Inthe exemplary embodiment of FIG. 8, the processors 70A and 70B areidentical in structure, and have a processor layout as depicted in FIG.7. In particular, the first processor 70A comprises an L3 cache 71A anL2 cache 72A, an execution unit 73A and an instruction unit 74A. Theexecution unit 73A includes a first floating point unit 75A and a secondfloating point unit 76A (wherein the first and second floating pointunits 75A and 76A are identical) and a set of floating point registers77A. Moreover, the second processor 70B comprises an L3 cache 71B an L2cache 72B, an execution unit 73B and an instruction unit 74B. Theexecution unit 73B includes a first floating point unit 75B and a secondfloating point unit 76B (wherein the first and second floating pointunits 75B and 76B are identical) and a set of floating point registers77B.

In one exemplary embodiment of the invention, the execution units 73Aand 73B of the first and second processors 70A and 70B are aligned toeach other and connected to each other using short vertical connections.With this structure, the execution units can be wired vertically so thatfor the two processors 70A and 70B shown in FIG. 8, the execution unit73A of the first processor 70A can functionally include one-half of theelements of the execution units 73A/73B of the processor pair, and theexecution unit 73B of the second processor 70B can functionally includethe other one-half of the elements of the execution units 73A/73B of theprocessor pair, wherein each pair of halves being is chosen so as tominimize the planar area of each execution unit.

This 3-D aggregation of execution units is advantageous overconventional planar geometries. In a conventional planar system, theexecution units of two processors lying in the same plane can beconnected such that the output of one execution unit can be input to thesecond execution unit. However, the “horizontal” electrical interconnectbetween the execution units of the two processors can be relatively long(e.g., 5 mm-20 mm) such that there may be one or two “dead” cycles inthe transmission of the signal between the processors, which results inan undesired delay in the signal transmission. In contrast, in the 3-Dstacked processor-on-processor architecture such as shown in FIG. 8,half of the elements of the execution units on each processor areeffectively aggregated into a new execution unit so that the executionunit in each plane is effectively smaller in area. Since the sameelements of each processor are spatially co-located, the area of theaggregated components of both processors is achieved by verticallyconnecting the execution unit elements across the 3-D layers.

For example, in the exemplary embodiment of FIG. 8, assume that eachprocessor 70A and 70B has two identical floating point units 75A/76A and75B/76B. In the first processor plane 70A, it may take 1-2 cycles oflatency to transmit a signal from the output of the first floating-pointunit 75A to the input of the second floating-point unit 76A because ofthe horizontal distance between the floating point units 75A and 76A.If, however, the co-located pair of first floating point units 75A and75B in both planes are vertically connected, and the co-located pairsecond floating point units 76A and 76B are vertically connected, thenthe execution unit 73A of the first processor 70A can utilize thevertically connected pair of first floating point units 75A and 75B, andthe execution unit 73B of the second processor 70B can utilize thevertically connected pair of second floating point units 76A and 76B, sothat the execution unit of each processor 70A and 70B still has twofloating point units.

The vertical connections between the processor elements 75A and 76A andprocessor elements 75B and 76B provide shorter paths in the processorfunction, and allow each processor 70A and 70B to be constructed usingelements from different planes of processors in the 3-D framework. Thiseffectively decreases the planar geometry of each processor and removesdead cycles from the execution flow as the path from the output of oneexecution element (on one plane) to the input of the execution element(on another plane) is much faster. These principles can be applied toother aligned components of the execution units, such as arithmeticunits, etc., as well as other processor elements such as the L2 an L3caches, as will be explained in further detail below.

In other exemplary embodiments of the invention as depicted in FIG. 8,each of the processors 70A and 70B can be used independently of eachother, wherein the vertical connections between the processor unitsacross the processor layers would not be used to aggregate or shareresources. For example, in one operating mode, both processors 70A or70B can run (typically on unrelated programs) at reduced power (e.g.,half power) so that the total power is substantially the same as itwould be if only one processor 70A or 70B was operated at one time atfull power. In another mode of operation, one of the processors 70A or70B can be turned off and the other can be operated in a high-speed mode(or turbo mode) at twice the power, for example.

In another exemplary embodiment of the invention, in an enhanced “Turbo”mode of operation, one of processors 70A or 70B can be disabled(inactive), and the other can be operated in a high-speed mode (or turbomode) at twice the power, but wherein certain elements of the executionunit of the inactive processor can be used by the active processorthereby enhancing its execution capabilities. For example, in theexemplary embodiment of FIG. 8, the second processor 70B (primaryprocessor) can be turned on and running with increased power in ahigh-speed turbo mode, while the first processor 70A can be turned off,but wherein the microarchitecture of the second (active) processor 70Bis augmented by using elements of the first (inactive) processor 70A Byway of specific example, the floating point units 75A and 76A andregisters 77A of the first (inactive) processor 70A can be utilized bythe execution unit 73B of the second (active) processor 70B whileoperating in enhanced turbo mode so the second processor 70B can operateat increased speed with four floating-point units 75A, 75B, 76A, 76B andadditional registers 77A. This augmented architecture allows the secondprocessor 70B to run code that is more powerful faster and moreefficiently. With this framework, the mode control scheme can beconfigured so that a given processor can be turned off, while allowingone or more components of the inactive processor to be selectivelypowered on and off by coupling or decupling power lines to the desiredcomponents of the inactive processor.

In another exemplary embodiment of the invention, different caches indifferent layers of processor chips can be conjoined using verticalconnections so that the processors can operate caches at any particularlevel in the cache hierarchy as a single shared cache. For example iftwo stacked processors have their L2 caches aligned and their L3 cachesaligned, then the aligned pair of L2 caches can be operated as a singleshared L2 cache having twice the capacity, and the aligned pair of L3caches can be operated as a single shared L3 having twice the capacity.These principles will now be explained in further detail with referenceto FIGS. 9A, 9B and 9C.

FIG. 9A is a schematic perspective view of a 3-D stacked multiprocessordevice 90 comprising a first processor 90A and a second processor 90Bvertically stacked on top of the first processor 90A. In the exemplaryembodiment of FIG. 9A, the processors 90A and 90B are identical instructure, and have respective processor cores 91A and 91B, L2 caches92A and 92B, and L3 caches 93A and 93B. As depicted in FIG. 9A, the L2caches 92A and 92B are aligned and have the same footprint (2D area).Moreover, the L3 caches 93A and 93B are aligned and have the samefootprint. In this 3-D stacked framework, the aligned L2 caches 92A and92B can be vertically connected and operated as a single shared L2cache. Moreover, the aligned L3 caches 93A and 93B can be verticallyconnected and operated as a single shared L3 cache.

For instance, FIG. 9B is a schematic perspective view of the 3-D stackedmultiprocessor device 90 of FIG. 9A, wherein the L3 caches 93A and 93Bare conjoined and can operated by one or both of the processors 90A and90B as a shared L3 cache 93A/B. Similarly, FIG. 9C is a schematicperspective view of the 3-D stacked multiprocessor device 90 of FIG. 9A,wherein the L2 caches 92A and 92B are also conjoined and can be operatedby one or both of the processors 90A and 90B as a shared L2 cache 92A/B.In particular, in one exemplary embodiment wherein the L2 and L3 cachesof the processors 90A and 90B are vertically connected together, the L2and L3 caches can be used in two alternative modes—either as independentcaches wherein the connections between them across layers are not used,or shared across the layers thereby enhancing the cache capacity of allthe processors in the layers.

An advantage to a 3-D stacked cache framework is that the storagecapacity of the caches is doubled without increasing the cache accesstime. Indeed, the speed of access to a cache is generally known to beproportional to the square root of the cache area. In the exemplaryembodiments shown in FIGS. 9B and 9C, vertically connecting the alignedL2 and L3 caches does not increase the cache area as the footprints ofthe corresponding L2 and L3 caches are spatially coincident. In thisregard, since area of the conjoined L2 caches 92A/B and the area of theconjoined L3 caches 93A/B does not increase by virtue of the verticalconnections, the cache access speed remains the same. In order to enableaccess to the same cache address space for the processors 90A and 90Brunning different programs, cache control schemes can be readilyimplemented to control and organize the shared cached directory and tomaintain cache coherence between the various cache layers.

In another exemplary embodiment of the invention, 3-D stacked processordevice can be constructed to include a plurality of processors that areconjoinable to increase a number of threads that are supposed by asingle processor image within the 3-D stack of processors. For example,in a 3-D stacked processor device comprising a first processor chiphaving a first processor, and a second processor chip having a secondprocessor, both the first and second processor chips can be active,wherein the first and second processors are configured to operate as asingle processor and aggregate their threads to increase an amount ofthreads that are usable by the first and second processors. This allowsthe multithreading capability of a single processor within the 3-Dstacked to be effectively increased without requiring overhead (threads)associated with having to employ additional threads on the singleprocessor itself. These principles will now be explained in further withreference to FIGS. 10 and 11.

FIG. 10 is a schematic perspective view of a 3-D stacked processordevice 100 comprising a first processor 100A and a second processor 100Bvertically stacked on top of the first processor 100A. In the exemplaryembodiment of FIG. 10, the first and second processors 100A and 100B aremultithreaded processors, and have identical processors and resistersets. In particular, the first processor 100A comprises four sets ofregisters 101A, 102A, 103A and 104A to implement four threads.Similarly, the second processor 100B comprises four sets of registers101B, 102B, 103B and 104B to implement four threads.

In the exemplary embodiment of FIG. 10, by vertically aligning andconnecting the processors 100A and 100B, the 3-D processor stack can beoperated in aggregation as a single multithreaded processor havingcorrespondingly more threads. For example, in the example of FIG. 10,the four threads 101A, 101B, 102A, 102B, 103A, 103B, 104A and 104B ofthe two processors 100A and 100B can be run jointly so that the 3-Dprocessor stack 100 appears to be a single processor running eightthreads. Independently, for system-level arbitration in 3-D, when two ormore processors are aligned, that set of processors will appear as asingle node in the system's arbitration scheme. In this way, anarbitration “tree” as discussed below, for example, does not grow incomplexity when additional processors are added in new stacked planes.

For a conventional planar system, processors can be fabricated with anincreasing number of independent register sets to implement more threadsthat can be concurrently operated to increase the processing capabilityfor multiple programs. However, as the number of threads per processorincreases, the planar dimensions of the processor increases, resultingin cycle delays in communications between the resister sets andprocessor execution units, as well as increased power. With a 3-Dstacked architecture such as shown in FIG. 10, the processors can besimplified with less register sets to support fewer threads perprocessor, while aggregating the thread between processor layers, asneeded to increase the overall number of threads that a given layer canutilize. For instance, assuming most workloads for a given applicationoperate with four or fewer threads, the processors 100A and 100B asshown in FIG. 10 can be optimized as four-thread processors. If a givenworkload requires more than four threads (up to 8 threads) to beexecuted, then the processors 100A and 100B within the 3-D processorstack 100 could be combined and operated as a single processor havingeight threads.

In the exemplary embodiment of FIG. 10, control schemes andcommunication path are implemented to support the aggregation of threadsacross the different layers and to connect the caches between the layersand maintain cache coherence. These control schemes are communicationpath are designed so that each of the processors will see the same statewhen the threads in different layers actually share their addressspaces. These concepts are schematically shown in FIG. 11.

In particular, FIG. 11 schematically illustrates communication pathsbetween various components of the processors shown in FIG. 10, accordingto an exemplary embodiment of the invention. As depicted in FIG. 11, thefirst processor 100A comprises a plurality register sets 101A, 102A,103A and 104A (also denoted T0, T2, T4 and T6, respectively) that areassociated with a first processor unit 105A, an L2 and L3 cache 110A, aninstruction cache 112A, and a data cache 114A. Similarly, the secondprocessor 100B comprises a plurality register sets 101B, 102B, 103B and104B (also denoted T1, T3, T5 and T7, respectively) that are associatedwith a second processor unit 105B, an L2 and L3 cache 110B, aninstruction cache 112B, and a data cache 114B.

The instruction caches 112A and 112B and data caches 114A and 114Breceive program instructions and data that are stored in the respectiveL2 or L3 caches 110A and/or 110B. The L2 and/or L3 caches 110A and/or110B can be conjoined and shared as discussed above with reference toFIG. 9C, for example. The program instructions that are stored in theinstruction caches 112A and 112B are executed by respective processors105A and 105B for one or more threads, and the execution state for agiven thread is stored in a respective one of the thread state registersT0, T1, T2, T3, T4, T5, T6, T7. As data is generated from execution ofthe program instructions, the processor 105A stores data in its datacache 114A and the processor 105B stores data in its respective datacache 114B. In accordance with principles of the present invention,additional communication paths 116 across the layers between theprocessors 105A and 105B and the data caches 114A and 114B are utilizedto facilitate consistent stores. This communication path 116 can beimplemented processor-on-processor, because the ports are spatiallycollocated when the processors are aligned.

Although the exemplary embodiments of FIGS. 10 and 11 illustrateprocessors each having register sets to support 4 operating threads,principles of the invention can be readily extended to each processorhaving n threads, wherein if each processor is n-way multithreaded, theprocessor pair can be run as a 2n-way multithreaded processor, as seenby the rest of the system. Again, with this implementation, it isparticularly useful when running n threads most of the time (where eachprocessor is not heavily threaded) and thereby allowing the basicprocessor to be optimized for n-thread operation, but having thecapability to extend the system to run 2 n threads when needed.

As noted above, when two or more processors are aligned in a 3-D stackedconfiguration, the processors will appear as a single node in thesystem's arbitration scheme. With this framework, an arbitration “tree”(or more generally, processor interconnect structure) can be constructedso that does not grow in complexity when additional processors are addedin new stacked planes. Exemplary processor interconnect structuresaccording to principles of the invention will now be discussed infurther detail with reference to FIGS. 12, 13, 14, 15, and 16.

FIG. 12 schematically illustrates a processor interconnect scheme for aplanar processor system. In particular, FIG. 12 illustrates a planarprocessor system 120 comprising a first processor 120A and a secondprocessor 120B that are disposed on the same plane. The first processor120A includes a plurality of processors P1A, P2A, P3A, P4A, P5A, P6A,P7A and P8A (collectively, PnA) and respective L3 caches. The processorsPnA of the first processor 120A communicate over a processorinterconnect structure 122A. Similarly, the second processor 120Bincludes a plurality of processors P1B, P2B, P3B, P4B, P5B, P6B, P7B andP8B (collectively, PnB) and respective L3 caches. The processors PnB ofthe second processor 120A communicate over a processor interconnectstructure 122B. In the example embodiment of FIG. 12, the processorinterconnect structures 122A and 122B are depicted as “tree” structuresthat implement a standard arbitration scheme.

Further, as depicted in FIG. 12, the communication busses 122A and 122Bare interconnected using an bus interconnect structure 124. In theplanar system 120 of FIG. 12, this bus interconnect structure 124 isrelatively long in the 2D plane. Accordingly to principles of theinvention, this processor interconnect structure can be more simplifiedin a 3-D stacked framework, such as depicted in FIG. 13. In particular,FIG. 13 schematically illustrates a processor interconnect scheme for a3-D stacked multiprocessor system according to an exemplary embodimentof the invention. In particular, FIG. 13 illustrates a planar processorsystem 130 comprising a first processor 130A and a second processor 130Bwhich is disposed on top of the first processor 130A. The firstprocessor 130A includes a plurality of processors P1A, P2A, . . . , P8A(collectively, PnA), which are interconnected and communicate using aprocessor interconnect structure 132A. Similarly, the second processor130B includes a plurality of processors P1B, P2B, . . . , P8B(collectively, PnB), which are interconnected and communicate using aprocessor interconnect structure 132B. The processor interconnectstructures 132A and 132B are depicted as “tree” structures thatimplement a standard arbitration scheme.

As further depicted in FIG. 13, the processor interconnect structures132A and 132B are interconnected using a connecting bus structure 134.The overall processor interconnect scheme of FIG. 13 is similar inconcept to the overall processor interconnect scheme of FIG. 12 exceptthat the bus connecting structure 134 (which connects the processorinterconnect structures 132A and 132B) is formed using verticalconnections between the stacked processor chips 130A and 130B. In thisregard, the vertical connecting bus structure 134 is much shorter inlength than the planar connecting bus structure 124 depicted in FIG. 12.As such, the overall processor interconnect scheme in FIG. 13 iseffectively smaller and faster than the overall processor interconnectscheme depicted in FIG. 12.

FIG. 14 schematically illustrates a processor interconnect scheme for a3-D stacked multiprocessor system according to another exemplaryembodiment of the invention. FIG. 14 schematically illustrates a 3-Dstacked processor structure 140 having a processor interconnectframework that is topologically equivalent to the processor interconnectframework of the 3-D stacked processor of FIG. 13, but faster and moresimplified in terms of size. More specifically, as shown in FIG. 14, aprocessor interconnect scheme is implemented using a tree structure 132Bon the second processor chip 130B and a plurality of vertical busconnections 141, 142, 143, 144, 145, 146, 147 and 148, which extend fromendpoints of the tree buss structure 132B on the second processor chip130B to respective processors on the first processor chip 130A. Theprocessor interconnect scheme of FIG. 14 takes into consideration thatthe processors on the first and second processor chips 130A and 130B arealigned to each other, such that the terminal end points of the tree busstructures 132A and 132B of the first and second processor chips 130Aand 130B (see FIG. 13) are also aligned. With this vertical alignment,the vertical bus connections 141, 142, 143, 144, 145, 146, 147 and 148(as shown in FIG. 14) can be implemented in place of the single verticalbus interconnect 134 (as shown in FIG. 13). Indeed, since each terminalpoint of the bus tree structure 132B on the upper processor chip 130B isaligned to the terminal point of the bus tree structure 132A on thelower processor chip 130A, the terminal points of the two treestructures 132A and 132B can be connected using short verticalconnections, which then allows one of the tree structures 132A and 132Bto be disregarded and not used. These principles are further discussedand illustrated with reference now to FIG. 15.

In particular, FIG. 15 is a schematic top perspective view of a 3-Dstacked multiprocessor system according to an exemplary embodiment ofthe invention having a processor interconnect structure that is based onthe processor interconnect structure scheme of FIG. 14. FIG. 15illustrates a 3-D stacked multiprocessor system 150 that is a physicalimplementation of the conceptual system shown in FIG. 14, wherein theprocessors PnA on the lower processor chip 130A and processors PnB onthe upper processor chip 130B are aligned with the terminal end pointsof the bus tree structure 132B. This allows the bus tree structure 132Bto be connected to pairs of processors P1A/P1B, P2A/P2B, P3A/P3B,P4A/P4B, P5A/P5B, P6A/P6B, P7A/P7B, and P8A/P8B at each end pointterminal of the buss tree structure 123B using short vertical conductivevia connections 141, 142, 143, 144, 145, 146, 147 and 148, respectively.Because these vertical conducive via interconnects are relatively short,each upper/lower pair of processors can be treated as a single verticaldrop on the global bus 132B. Again, the use of the vertical vias 141,142, . . . , 148 provide shorter communication paths between alignedprocessors, as compared to the single vertical buss connect structure134 shown in FIG. 13.

FIG. 16 schematically illustrates a processor interconnect structure fora 3-D stacked multiprocessor system according to yet another exemplaryembodiment of the invention. FIG. 16 schematically illustrates a 3-Dstacked processor structure 160 having a bus framework that is similarto that of FIG. 14, except for the inclusion and use of an additionaltree structure 162A on the lower processor chip 130A. The additionaltree structure 162A can be used to shorten the communication pathbetween in-plane processors and augment communication bandwidth. Inparticular, in the exemplary embodiment of FIG. 16, the tree structure162A can be used for processor-to-processor communication betweenprocessors PnA on the first processor chip 130A without having to usethe short vertical buss interconnects 141, 142, . . . , 148 or the uppertree structure 132B. Similarly, the tree structure 132B can be used forprocessor-to-processor communication between processors PnB on thesecond processor chip 130B without having to use the short vertical bussinterconnects 141, 142, . . . , 148 or the lower buss tree structure162A.

In another control scheme, both tree structures 162A and 132B can beused concurrently in conjunction with the short vertical interconnects141, 142, . . . , 148 to provide two independent communication pathsbetween any two processors so that 2× increase in communicationbandwidth may be realized. Indeed, assume that each tree structure 132Band 162A is a 16-byte bus, which requires 16 cycles to communicate 256bytes of information between processors. In this embodiment, thecommunication bandwidth can be increased to 32 bytes by concurrentlyusing two separate communication paths between any two processors tosend 32 bytes (16 bytes per path) at same time, thereby increasingcommunication bandwidth to 512 bytes of information for 16 cycles.

In another exemplary embodiment of the invention, a 3-D stackedmultiprocessor device can be constructed to include a plurality ofprocessors that are conjoinable and configured as a single hyper-fastprocessor by selectively combining the fastest components of eachvertically stacked processor. With advanced technology, there can beconsiderable variation in device performance between identicalprocessors, wherein some subsystems of one processor may be faster thanthe same subsystems of another identical processor, while at the sametime, the relationship could be the opposite for different subsystems.Indeed, based on variations of device dimensions and shapes, and dopingvariations, etc., a set of identical processors that are formed on givenwafer, having identical layout and macro functional components, can havefaster or slower components than the same components of anotheridentical processor.

In this regard, in accordance with another exemplary embodiment of theinvention, when two processors (a first and second processor) ondifferent layers of processor chips have an identical layout ofsubsystem regions, in one mode of operation, the first and secondprocessors can be configured to operate as a single processor bycombining faster ones of corresponding subsystem regions of the firstand second processors and by turning off slower ones of correspondingsubsystem regions of the first and second processors. These principleswill now be illustrated and discussed in further detail with referenceto FIGS. 17A and 17B.

In particular, FIG. 17A schematically illustrates two processors havingidentical layouts according to an exemplary embodiment of the invention,wherein corresponding regions of the two identical processors areidentified as being faster or slower than its counterpart region. Inparticular, FIG. 17A illustrates two identical processors 170A and 170having eleven identical major regions (macros) R1, R2, R3, R4, R5, R6,R7, R8, R9 and R11. After fabrication, these regions of the processorare tested for speed because while the processors are the same, someregions of a given will be faster/slower than the same region of anotheridentical processor. In the exemplary embodiment of FIG. 17A, regionsR1, R2, R4, R6, R8, R9 and R11 of the first processor 170A areidentified as being faster (labeled “F”) than the same regions on theidentical processor 170B. Moreover, regions R2, R5, R7, and R10 of thesecond processor 170B are identified as being faster (labeled “F”) thanthe same regions on the identical processor 170A.

FIG. 17B a schematic view of a 3-D stacked multiprocessor system 170according to an exemplary embodiment of the invention which includes theprocessors 170A and 170B of FIG. 17A. In particular, FIG. 17Bschematically illustrates a 3-D stacked processor structure that isformed by vertically stacking the two processors shown in FIG. 17A, andoperated as a single processor that is composed of the fastest of thecorresponding regions of each processor, according to an exemplaryembodiment of the invention. In FIG. 17, the processors are aligned andvertically connected such that corresponding regions R1, R2, . . . , R11are aligned and connected to each other. The caches and executionresources of the two processors 170A and 170B are vertically connectedso that the 3-D stacked processor system 170 can be operated in one of aplurality of modes.

For instance, in one mode, the processors 170A and 170B can be operatedas independent processors wherein each processor is active and operatingat half power, as discussed above. In another exemplary embodiment, oneof the processors 170A or 170B can be operated at full power or enhancedpower (Turbo Mode), while the other processor is turned off. In yetanother embodiment, the processors 170A and 170B can be operated as asingle processor that includes those regions from each processor thatare identified as being the fastest version of that region, so that theresulting processor can operate as a single ultrafast processor with aspeed that is faster than if using all the components from just oneprocessor layer. For instance, in the exemplary embodiment of FIG. 17B,the 3-D stacked processor structure 170 can be operated as a singleprocessor comprising 11 regions consisting of the fast regions R1, R2,R4, R6, R8, R9 and R11 of the first processor 170A and the fast regionsR2, R5, R7, and R10 of the second processor 170B.

In another exemplary embodiment of the invention, a 3-D stackedmultiprocessor device can have a plurality of conjoined processors thatoperate logically as a single processor image, but wherein at least oneprocessor is utilized for a “run-ahead” functionality. In particular, byway of example, in a 3-D stacked multiprocessor device having first andsecond stacked processors that are aligned and vertically connected toeach other, the first processor can be a primary processor that isresponsible for the architected state of the machine, and the secondaryprocessor can run ahead of the primary processor to resolve branches andgenerate misses early, while the secondary processor is unconstrained bythe architecture or program and unable to change the architected stateof the machine.

In this exemplary embodiment, the caches and execution resources of thefirst and second processors are connected together so they can be used,for example, in two alternative modes—either as independent processorswherein the connections between the processor layer are not used, or ina collaborative manner, wherein the primary processor executes programsand the secondary processor runs a simpler version of the programs sothat the secondary processor can advance ahead of the primary processorgenerating memory requests and resolving branches whose outcome can beused by the primary processor to avoid long-latency memory accesses andbranch mispredictions, among other options. This concept of implementinga run-ahead or assist-thread in a 3-D stacked processor system will bedescribed in further detail with reference to FIG. 18.

In particular, FIG. 18 schematically illustrates a method forimplementing run-ahead functionality in a 3-D stacked processor systemaccording to an exemplary embodiment of the invention. In particular,FIG. 18 illustrates a plurality of operations 181 and 182 that areperformed by a primary processor operating a main thread with regard toa memory that is shared between the primary and a secondary processor,and a plurality of operations 184, 185, 186, 187, 188 and 189 that areperformed by the secondary processor operating as run-ahead thread incollaboration with the primary processor.

In particular, as shown in FIG. 18, when executing a program in the 3-Dstacked processor system, the primary processor fetches instructions 181from memory 183 and executes every program instruction 182. Whileexecuting instructions, the primary processor will fetch and storeprogram data from the shared memory 183 and maintain the state of themachine (storage) that is visible to all outside entities. In otherwords, the primary processor executes the program correctly in that theprimary processor performs the instruction operations in the correctorder, and only manifests state change information to the rest of thesystem when those changes are known to be correct. However, to make theprogram execution faster, with higher instruction-level parallelism, thesecondary processor operates as a “run-ahead processor, wherein thesecondary processor does not guarantee correct and legal operation, anddoes not manifest state changes to the rest of the system. Instead, itruns as fast as possible in a speculative manner, and not bothering withinstructions that have nothing to do with the program flow. By operatingin this manner, the run-ahead processor will resolve many of thebranches and generate many necessary cache misses earlier than theprimary processor would be able to. This will allow the primaryprocessor to run faster than it normally would.

In particular, as shown in FIG. 18, the secondary processor will fetchinstructions 184 from the shared memory 183 and execute certaininstructions, such as data fetch instructions, and fetch data 185 fromthe shared memory 183 in response to the data fetch instructions. Thesecondary processor will execute data store instructions and perform amemory access operation 186 to determine if necessary data is stored inmemory 183. The secondary processor will execute simple instructions 187and execute branch instructions 188, and discard or otherwise ignore allother fetched instructions 189 that have no relation to determiningcaches misses or resolving branch redirections. In step 186, when thesecondary processor sees a data store instruction coming up, thesecondary processor will determine if a cache line exists for the datato be stored. If a cache line does not exist, the secondary processorwill generate a cache miss and proceed to have a cache line allocatedfor the data store and obtain the proper permissions to store the datain the newly allocated cache line (i.e., make sure the status of the newcache line is in a “data store ready” state). If the cache line doesalready exist, the secondary processor will determine if the cache lineis in a “data store ready” state, and proceed to obtain the properpermissions if not. In this manner, when the primary processor executesthe data store instruction, the cache line will be available and in“store ready” status, thereby avoiding a cache miss in the executionflow.

The secondary processor (run-ahead processor) accelerates the primaryprocessor by resolving contingencies before the primary processor seesthem. The secondary processor can operate in this matter as it does nothave to execute every instruction, and does not have to perform programoperations correctly. In the 3-D stacked configuration, since theprimary and secondary processors are spatially coincident and connectedby short vertical connections, they are able to share and view theexecution state, and otherwise synchronize more readily and robustlythan in a coplanar configuration, where long wires would be needed toexchange the proper synchronization information. Even with coplanarwiring between coplanar processors, the coplanar processors would likelynot be able to view each other's states coincidentally. In a 3-D stackedconfiguration, communications and interactions between the assist threadand main thread to share values and otherwise synchronize process flow,are more readily realizable through short vertical connections betweenthe resources of the primary and secondary processors.

In another exemplary embodiment of the invention, a 3-D stackedmultiprocessor device can have a plurality of conjoined processors whichoperate logically as a single processor image, but wherein at portionsof their Architected Storage operate as a Private Storage Space (orscratchpad space) that is not accessible to processor outside the 3-Dstack. In other words, multiple processors can be conjoined into asingle operating entity (a “processor” as seen from the outside) havingan area of private storage that can be used for scratchpad space, and toorganize other data structures, wherein the private storage is notvisible to the other operating entities in the system. When a tuple ofprocessors is run as a single logical processor in either run ahead modeor Hyper turbo mode, or any other tupling, one or more of the caches ofthe tuple can be used as private storage with an application-specificstructure.

Although exemplary embodiments of the present invention have beendescribed herein with reference to the accompanying figures, it is to beunderstood that the invention is not limited to those preciseembodiments, and that various other changes and modifications may bemade therein by one skilled in the art without departing from the scopeof the appended claims.

What is claimed is:
 1. A method for operating a computer processorcomprising a first processor chip and a second processor chip connectedin a stacked configuration; wherein the first processor chip comprises afirst processor, wherein the second processor chip comprises a secondprocessor, wherein the first and second processors are verticallyaligned and connected through vertical connections, the methodcomprising: configuring the vertically aligned first and secondprocessors to operate as a single logical processor; generating, by acontrol system, different sets of configuration parameters to operatethe single logical processor in different power operating modes;generating, by the control system, a first control signal to selectivelyinput a first set of the configuration parameters to the single logicalprocessor; utilizing, by the single logical processor, the first set ofthe configuration parameters to operate the single logical processor ina first power operating mode wherein the first processor is turned onand the second processor is turned off; generating, by the controlsystem, a second control signal to selectively input a second set of theconfiguration parameters to the single logical processor; and utilizing,by the single logical processor, the second set of the configurationparameters to operate the single logical processor in a second poweroperating mode wherein both the first processor and the second processorare turned on; wherein in the second power operating mode, both thefirst processor and the second processor operate at less than full powerso that a total power of the single logical processor in the secondpower operating mode is substantially the same as a total power of thesingle logical processor in the first power operating mode when only thefirst processor is turned on and operating at full power.
 2. The methodof claim 1, wherein the first processor and the second processor aresubstantially the same.
 3. The method of claim 1, wherein in the firstpower operating mode, the first processor of the single logicalprocessor is turned on and operating at full power.
 4. The method ofclaim 1, wherein in the second power operating mode, the first andsecond processors of the single logical processor each operate at about50% of its maximum power.
 5. The method of claim 1, wherein the firstand second sets of the configuration parameters serve to modulate apower supply voltage level applied to the first and second processors.6. The method of claim 1, wherein the first and second sets of theconfiguration parameters serve to modulate an operating frequency of thefirst and second processors.
 7. A method for operating a computerprocessor comprising a first processor chip and a second processor chipconnected in a stacked configuration, wherein the first processor chipcomprises a first processor, wherein the second processor chip comprisesa second processor, wherein the first and second processors arevertically aligned and connected through vertical connections, themethod comprising: configuring the vertically aligned first and secondprocessors to operate as a single logical processor; generating, by acontrol system, different sets of configuration parameters to operatethe single logical processor in different power operating modes;generating, by the control system, a first control signal to selectivelyinput a first set of the configuration parameters to the single logicalprocessor; utilizing, by the single logical processor, the first set ofthe configuration parameters to operate the single logical processor ina first power operating mode wherein the first processor is turned onand the second processor is turned off; generating, by the controlsystem, a second control signal to selectively input a second set of theconfiguration parameters to the single logical processor; and utilizing,by the single logical processor, the second set of the configurationparameters to operate the single logical processor in a second poweroperating mode wherein both the first processor and the second processorare turned on.
 8. The method of claim 7, wherein the first processor andthe second processor are substantially the same.
 9. The method of claim7, wherein in the first power operating mode, the first processor of thesingle logical processor is turned on and operating at full power. 10.The method of claim 7, wherein in the second power operating mode, thefirst and second processors of the single logical processor each operateat about 50% of its maximum power.
 11. The method of claim 7, whereinthe first and second sets of the configuration parameters serve tomodulate a power supply voltage level applied to the first and secondprocessors.
 12. The method of claim 7, wherein the first and second setsof the configuration parameters serve to modulate an operating frequencyof the first and second processors.